Distinguished Engineer - Digital Design

Job Title

Distinguished Engineer - Digital Design

Role Summary

Lead technical design for custom SoC/ASIC projects in Marvell's Custom Compute Solutions Business Unit, establishing and growing a San Diego design center. Responsible for micro-architecture, RTL implementation, verification strategy, and cross-functional integration to deliver customer silicon for advanced AI and compute platforms.

Opportunity to define design strategy and build a new local engineering team and methodology.

Experience Level

Senior. Experience guidance provided in the posting: Bachelor's +17+ years; Master's +12–15+ years; PhD +10–12+ years (requirements vary by degree).

Responsibilities

Primary responsibilities include defining micro-architecture, implementing RTL, coordinating verification, and supporting physical implementation and post-silicon activities.

• Define micro-architecture and write specifications for complex SoC blocks.
• Implement RTL using low-power coding techniques and SystemVerilog.
• Collaborate with verification on test plans, coverage, full-chip simulation, and debug.
• Develop SVA assertions for dynamic simulation and formal verification.
• Prepare and present design reviews; provide schedule estimates and contingency plans.
• Work with physical design to aid implementation of functional blocks and support timing closure.
• Coordinate with project management and cross-site teams to shape methodology and delivery.
• Support post-silicon bring-up and provide expert product support during debug.
• Work with software teams to ensure products meet customer use cases.

Requirements

Must-have technical skills and experience:

• Fluent in SystemVerilog RTL coding techniques.
• Experience in high-speed, multi-clock-domain designs.
• Expertise with PCIe and CXL protocols.
• Familiarity with modern SoC architectures and interfaces (AXI, DDR, Ethernet, PCIe).
• Micro-architecture experience for custom/ASIC products involving chip I/O, shared memory, and embedded processors.
• RTL design, synthesis, static-timing closure, formal verification, gate-level simulation, and block-level functional verification experience.
• Ability to create SVA assertions and apply formal verification tools and concepts.
• Hands-on front-end chip-development experience and proficiency with design tools and methodologies.
• Experience supporting post-silicon debug and integrating with software teams.
• Strong verbal and written communication; discipline in documentation.
• Ability to work effectively across multiple sites and provide technical leadership.

Nice-to-have:

• Experience designing >1 GHz/high-performance embedded-processor SoCs.
• Experience with implementation and timing closure for high-speed designs.
• Scripting skills (Python, Perl, Tcl, UNIX shell).

Education Requirements

Posting specifies degree-based options: Bachelor's degree in Computer Science, Electrical Engineering, or related field with 17+ years of related professional experience; OR Master's degree in CS/EE or related with approximately 12–15+ years experience; OR PhD in CS/EE or related with approximately 10–12+ years experience. The posting allows equivalent practical experience as an alternative.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.