Display Engineering Intern

Job Title

Display Engineering Intern

Role Summary

Work in Reality Labs to develop pre-silicon simulation and array-level models for high pixel-density display arrays, predicting front-of-screen artifacts such as crosstalk and mura. Collaborate with panel design, optical engineering, and test teams to improve model accuracy and correlate simulations with measured display data.

This is a 12-week internship based in Sunnyvale, CA.

Experience Level

Entry-level internship; intended for current graduate students (MS or PhD) who will return to their degree program after the internship.

Responsibilities

Primary responsibilities include circuit and array modeling, simulation, measurement, and data analysis.

• Design semiconductor circuits using Cadence Virtuoso Schematic Editor and simulate with Spectre/SPICE.
• Build and validate large-array simulation models using combined distributed and lumped loads and peripheral circuit blocks.
• Analyze circuit layouts and incorporate parasitic extraction into array-level models to predict coupling to sensitive nodes.
• Correlate simulated predictions (crosstalk, mura, settling behavior, power/load effects) with measured display data to improve model accuracy.
• Operate optical lab instruments (microscope, spectrometer, imaging colorimeter, probe station) to measure display KPIs.
• Develop quantitative metrics for display artifacts and automate measurement and data analysis using Python or MATLAB.

Requirements

Must-have technical skills and authorization requirements.

• Experience in mixed-signal circuit design, including analog/digital fundamentals and semiconductor device behavior.
• Hands-on experience with Cadence Virtuoso (Schematic Editor) and Cadence circuit simulation (Spectre/SPICE).
• Understanding of circuit layouts, parasitic effects, and large-array modeling concepts.
• Proficiency in Python and/or MATLAB for data collection, automation, and analysis.
• Must obtain and maintain work authorization in the country of employment at the time of hire.

Nice-to-have:

• Background in memory design and characterization or related array structures (e.g., SRAM, image sensors).
• Familiarity with display technologies and pixel circuits (LCD, OLED, uOLED, multi-transistor pixel architectures).
• Experience developing quantitative optical/visual performance metrics for displays.

Education Requirements

Required: currently enrolled in or pursuing a Master of Science (MS) in Electrical Engineering, Microelectronics, VLSI, or a related field. Preferred: currently enrolled in or pursuing a PhD in Electrical Engineering, Microelectronics, VLSI, or a related field. Candidates must intend to return to a full-time degree program after completing the internship.

About the Company

Company: Meta Platforms

Headquarters: Menlo Park, California, United States

American technology company that develops social networking products (Facebook, Instagram, WhatsApp) and invests in virtual/augmented reality hardware and software through Reality Labs, focusing on connectivity, advertising, and immersive computing experiences.