Director, Engineering (GPU Physical Design)

Job Title

Director, Engineering (GPU Physical Design)

Role Summary

Lead and deliver physical implementation for high-performance GPU cores. Own floorplanning, place-and-route, timing closure, power optimization and physical verification while managing a small team of engineers and coordinating across design, DFT and verification groups.

Experience Level

Senior-level. The posting expects an experienced director: typically 20+ years in physical design/implementation with 10+ years leading teams (the posting also lists alternative degree-linked experience minimums).

Responsibilities

Responsibilities focus on technical leadership of GPU physical design and delivering PPA and timing goals.

• Lead physical implementation for high-performance GPU cores: floorplanning, place-and-route, CTS, timing closure, and power optimization.
• Drive physical verification (DRC/LVS), PDN analysis, and formal verification activities as needed.
• Make PPA trade-off decisions for PPA-critical cores and ensure timing convergence for high-frequency datapaths.
• Oversee block-level PnR convergence using Synopsys ICC2 / Cadence Innovus and STA with Tempus/PTS I or equivalent tools.
• Define and validate clocking architecture and constraints; resolve STA and timing sign-off issues.
• Collaborate closely with RTL design, DFT, verification and PNR teams to drive deliveries to schedule.
• Manage, mentor, and coordinate a small team to meet project milestones and technical deliverables.
• Maintain and develop automation scripts (Tcl/Perl) to improve design-flow productivity.

Requirements

Key must-have skills and experience for this role; education requirements are listed separately below.

• Must-have: 20+ years of experience in Physical Design / Implementation and ~10+ years leading teams on high-performance cores (as stated in the posting).
• Deep expertise in timing convergence for high-frequency, datapath-intensive cores and advanced STA methodologies.
• Proven experience with Synopsys ICC2 or Cadence Innovus for place-and-route, and Tempus/PTSI (or equivalent) for timing sign-off.
• Hands-on experience with floorplanning, PnR, CTS, PDN, timing closure, power optimization, and physical verification flows (DRC/LVS).
• Strong scripting skills (Tcl/Perl) and familiarity with flow automation.
• Excellent problem-solving and communication skills; ability to work cross-functionally and meet project deadlines.
• Nice-to-have: Specific GPU core implementation experience, advanced-node experience, formal verification exposure, low-power/voltage optimization experience.

Education Requirements

Degree expected: Bachelor's, Master's, or PhD in Science, Engineering or related fields (examples: Electrical/Electronic Engineering, Computer Engineering, Computer Science). The posting lists equivalencies: Bachelor's + 8+ years, Master's + 7+ years, or PhD + 6+ years; in another section the role cites 20+ years of physical design experience and 10+ years leading teams. Equivalent practical experience is acknowledged by the posting's alternative experience-based minima.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.