Director, Design Verification - MEM/PCIE COE

Job Title

Director, Design Verification - MEM/PCIE COE

Role Summary

Lead and manage design verification for Marvell's memory and PCIe chip families. Own DV, emulation and pre-silicon verification strategy and execution, and coordinate delivery across cross-functional SoC teams.

Work with Architecture, Design, DFT, PD, Firmware and system teams to ensure designs meet customer specifications and product schedules.

Experience Level

Senior (Director). Preferred 20+ years of relevant experience, or 15+ years with an advanced degree.

Responsibilities

The role leads verification strategy, execution and team development. Key responsibilities include:

• Lead DV, emulation and pre-silicon verification execution with a zero-defect mindset.
• Define verification scope, methodology, testbench architectures and execution timelines; monitor progress and mitigate risks.
• Drive DV tool evaluation and selection and implement productivity improvements.
• Collaborate with Architecture, Design, DFT, PD, Firmware and system teams for successful product delivery.
• Hire, build, develop and retain a high-performance verification engineering team; address training and development needs.
• Monitor industry DV trends and adapt verification approaches accordingly.
• Set goals, track metrics and report status to stakeholders.

Requirements

Must-have technical and leadership qualifications:

• Strong understanding of the ASIC development process and SoC architecture.
• Proven ability to lead ASIC development and verification teams and deliver complex silicon.
• Experience with processor cores, memory subsystems and peripheral interfaces.
• Demonstrated track record of delivering high-quality ASICs.
• Excellent communication, interpersonal and presentation skills and strong cross-functional leadership.
• Highly motivated, self-driven, and curious about new technologies.
• Experience with verification methodologies, emulation and pre-silicon verification tools.
• Nice-to-have: practical knowledge of PCIe architectures and memory technologies (DDR, LPDDR, HBM).

Education Requirements

Bachelor's degree in Computer Engineering, Electrical Engineering or a related field with 20+ years of related professional experience; or a Master's degree or PhD in Computer Science, Electrical Engineering or related fields with 15+ years of experience; or equivalent practical experience.

Expected Base Pay Range (USD): 195,180 - 292,400 per annum.

Apply: Marvell application page

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.