Digital Design Verification Principal Engineer

Job Title

Digital Design Verification Principal Engineer

Role Summary

Lead the development and deployment of unified digital IP and SoC verification methodologies and scalable verification infrastructure. The role sits on the Digital IP Verification Methodology (COE) team and partners with global engineering and tool teams to improve verification efficiency and quality.

Focus areas include applying agentic AI to accelerate verification, implementing reference flows using Synopsys EDA tools, mentoring engineers, and driving technical initiatives that influence product and methodology evolution.

Experience Level

Senior — minimum 12+ years of hands-on IP/SoC verification experience with proven technical leadership.

Responsibilities

Primary responsibilities include defining and delivering verification methodology, infrastructure, and best practices across IP and SoC projects.

• Apply agentic AI techniques to accelerate verification plan generation, testcase creation, coverage analysis, and debug artifacts.
• Implement and maintain reference and unified verification flows for Synopsys digital IP using tools such as VCS, Verdi, VMS Execution Manager, Verdi Planner (HVP), and VIPs.
• Design and build robust, scalable verification infrastructures to support complex IP and SoC projects.
• Partner with global engineering teams to define, document, and propagate verification methodologies and standards.
• Lead and mentor junior engineers, promoting technical growth and collaboration.
• Independently manage high-impact technical initiatives and ensure timely, high-quality deliverables.
• Collaborate with tool development teams to influence product evolution and optimize verification workflows.
• Support customers and internal stakeholders by troubleshooting and refining verification processes and flows.

Requirements

Must-have technical skills and experience; items listed as nice-to-have are indicated.

• Minimum 12+ years of hands-on IP/SoC verification experience with substantial technical contributions.
• Good understanding of agentic AI technologies, specifically Cursor and/or VS Code co-pilot, and willingness to apply these to verification workflows.
• Familiarity with Synopsys verification tools: VCS, Verdi, VMS Execution Manager, Verdi Planner (HVP), and VIPs.
• Proven ability to validate verification flows and infrastructure for complex digital designs.
• Strong programming and scripting skills (SystemVerilog, UVM, Tcl, Python, or similar).
• Experience managing technical projects and delivering independently across multiple tasks.
• Ability to document, communicate, and propagate technical methodologies across global teams.
• Nice-to-have: exposure to agentic AI EDA tools and prior experience influencing EDA tool development and integration.

Education Requirements

Bachelor's or Master's degree in Electrical, Electronics, or Computer Engineering.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.