Digital Design Lead - STA

Job Title

Digital Design Lead - STA

Role Summary

The Digital Design Lead - STA will drive timing-closure and static timing analysis activities for high-speed mixed-signal communication ASICs. The role involves RTL implementation, synthesis, timing closure, verification and debugging of high-performance digital circuits that interface with analog subsystems.

This position works within a cross-functional design team and requires coordination with architecture, RTL, DFT, verification and layout teams to meet performance, power and area goals.

Experience Level

Level - Senior. Posting specifies a minimum of 3+ years of relevant experience.

Responsibilities

Primary responsibilities focus on implementation, timing closure and verification of high-speed communication designs and on collaborating with other engineering disciplines to deliver silicon-ready designs.

• Implement and maintain RTL; perform simulation, synthesis and timing analysis.
• Perform static timing analysis (STA) and lead timing-closure efforts across synthesis, placement, CTS and signoff stages.
• Verify, evaluate and debug designs at both behavioral and circuit levels.
• Prepare test methods, specifications, application information, data sheets and demo board support.
• Plan and organize multiple tasks to meet schedule and quality objectives; propose solutions to complex design problems.
• Coordinate and communicate with analog and digital design teams; participate in work groups and design reviews.

Requirements

Must-have technical skills and experience, plus preferred skills that strengthen candidacy.

• Must-have: 3+ years of relevant experience; thorough understanding of timing-closure methodologies and STA.
• Must-have: Practical experience with RTL coding, simulation, synthesis, verification and debugging of high-speed communication designs.
• Must-have: Systematic problem-solving and ability to work with general instructions on routine tasks and detailed instructions on new assignments.
• Preferred: Experience defining and driving SoC timing-closure strategy across synthesis, placement, CTS and signoff.
• Preferred: Ability to collaborate with architecture, RTL, DFT and verification teams to preserve design intent.
• Preferred: Experience driving ECO implementation for functional and timing fixes; analyzing PPA trade-offs using advanced EDA tools.
• Preferred: Knowledge of DFT and basic layout aspects; interest in applying AI/ML techniques and flow automation.

Education Requirements

Degree Level: Bachelor's Degree (as stated in the posting).

About the Company

Company: Texas Instruments

Headquarters: Dallas, Texas, USA

Texas Instruments is a global semiconductor company that designs, manufactures, and sells analog and embedded processing chips for various markets including industrial, automotive, and personal electronics. The company's innovations aim to make electronics more affordable and reliable, fostering advancements in technology through each generation of semiconductors.