Digital Design Engineer, Interconnect
Meta PlatformsJob Title
Digital Design Engineer, Interconnect
Role Summary
Design engineer focused on interconnect/NoC/fabric IP and subsystem microarchitecture for production SoCs. Work across architecture, RTL, verification, and physical design to deliver low-power, high-performance interconnect solutions for volume silicon.
The role involves micro-architecture definition, RTL development, performance/power trade-off analysis, and cross-functional integration to meet area, power, and frequency targets.
Experience Level
Senior - typically 8+ years of hardware design experience with production silicon shipped in volume.
Responsibilities
Key responsibilities include design, implementation, and cross-team integration of interconnect IP and subsystems.
- Define and implement ASIC digital micro-architecture for interconnect/fabric IP.
- Develop RTL and participate in design verification for complex IPs and subsystems.
- Perform performance, timing, and power analysis; drive design changes to meet targets.
- Collaborate with architects to map algorithms and specify IP/subsystem requirements.
- Work closely with Verification, Physical Design, and Design-for-Test teams to integrate designs into SoC flows.
- Drive micro-architecture and RTL delivery for IP/sub-systems; mentor and technically lead engineers across deliverables.
Requirements
Must-have technical qualifications and relevant experience. Preferred items are listed separately.
- 8+ years as a hardware/digital design engineer with production silicon shipped in volume.
- Proven experience in digital micro-architecture, RTL coding, and micro-architecture development.
- Experience communicating technical design decisions and trade-offs to verification, physical design, and architecture teams.
- Experience collaborating with physical design and timing partners on implementation details such as pipelining, physical partitioning, clock/power-domain crossings, and repeater strategies.
- Experience defining fabric architecture and microarchitecture: topology, address mapping, ordering/coherency, buffering, QoS, arbitration, and virtual channels; performance modeling and traffic-driven budgeting.
Nice-to-have / Preferred:
- Experience with interconnect configurator/generation flows and technically leading deliverables.
- Demonstrated history developing interconnect/NoC/fabric IP from architecture through RTL delivery.
- Experience integrating AI tools to optimize workflows and applying responsible AI practices.
Education Requirements
Bachelor's degree in Computer Science, Computer Engineering, or a relevant technical field, or equivalent practical experience.
About the Company
Company: Meta Platforms
Headquarters: Menlo Park, California, United States
American technology company that develops social networking products (Facebook, Instagram, WhatsApp) and invests in virtual/augmented reality hardware and software through Reality Labs, focusing on connectivity, advertising, and immersive computing experiences.
