DFx/Diagnosis Engineer

Role Summary

Lattice Semiconductor is looking for a Senior DFx/Diagnosis Engineer to join the Manufacturing team, focusing on DFx Design. This position offers the opportunity to contribute to a dynamic team with room for personal and professional growth.

Experience Level

Senior level position; specific years of experience not specified.

Responsibilities

Key responsibilities include:

• Define scan methodology, architecture, and implementation strategies for FPGA SoC.
• Perform top/block-level ATPG generation and pattern simulation.
• Collaborate with cross-functional teams to ensure optimal trade-offs.
• Verify DFT circuitry while debugging timing simulation issues.
• Enhance backend ATPG initiatives and work with front-end teams for product success.
• Refine ATPG processes applying optimization techniques for FPGA.
• Drive high test coverage through structural and specific IP tests to meet product quality and DPM objectives.

Requirements

Applicants should meet the following criteria:

• Extensive experience in DFT architecture and methodology.
• Knowledge of test models, pattern generation, verification, and fault simulation.
• Practical experience with DFT scan insertion and ATPG processes.
• Familiarity with EDA tools including Tessent, Synopsys, and Cadence.
• Experience in silicon debug and pattern delivery for sub-systems or SOCs.
• FPGA DFT methodology experience is advantageous.

Education Requirements

Not specified.

About the Company

Company: Lattice Semiconductor

Headquarters: Portland, Oregon, USA

Lattice Semiconductor specializes in low power, small-form-factor programmable logic devices and solutions. The company is known for its innovative technology that enables a wide range of applications, including communication, consumer, and industrial markets.