CaritaTech logo

DFT Engineer

CaritaTech
May 28, 2026
Full-time
Remote friendly (Santa Clara, California, United States)
Worldwide
DFT Jobs, Level - Mid-Career

Job Title

DFT Engineer

Role Summary

Responsible for implementing and validating Design-for-Test (DFT) methodologies for advanced ASIC/SoC products to improve testability and manufacturing quality. Works within the SoC engineering team and coordinates with RTL, Physical Design, and Verification groups.

Position is onsite/hybrid in Santa Clara, CA and focuses on pre-silicon DFT implementation and post-silicon test support.

Experience Level

Mid-level β€” experience listed as 3–12 years.

Responsibilities

Primary duties include designing, implementing, and validating DFT solutions and supporting silicon bring-up.

  • Develop and implement DFT architectures for complex ASIC/SoC designs.
  • Perform scan insertion, ATPG, MBIST, LBIST, and boundary-scan implementation.
  • Run fault-coverage analysis and generate test patterns.
  • Collaborate with RTL, Physical Design, and Verification teams on testability and integration.
  • Debug DFT-related issues during simulation and silicon bring-up.
  • Support compression techniques and low-power DFT methodologies.
  • Validate test structures and support post-silicon activities and bring-up.
  • Ensure required test coverage and quality metrics for tapeout.

Requirements

Must-have technical skills and experience required for the role; preferred items listed separately.

  • Must-have: Strong understanding of DFT concepts and methodologies.
  • Must-have: Hands-on experience with scan, ATPG, JTAG, MBIST, and compression flows.
  • Must-have: Experience with DFT tools such as Tessent, SpyGlass DFT, Modus, or Tetramax.
  • Must-have: Knowledge of Verilog/SystemVerilog and simulation/debug flows.
  • Must-have: Familiarity with semiconductor design and test processes.
  • Must-have: Scripting experience in Tcl, Perl, or Python.
  • Nice-to-have: Experience with advanced process nodes and large SoC designs.
  • Nice-to-have: Understanding of low-power DFT techniques.
  • Nice-to-have: Prior silicon debug and bring-up experience.
  • Nice-to-have: Strong analytical and communication skills.

Education Requirements

Not specified.


About the Company

Company: CaritaTech

Engineering staffing and consulting firm providing placement and contract services for hardware, semiconductor, and embedded systems professionals, including roles in SoC/ASIC physical design and verification.

CaritaTech logo

Date Posted: 2026-05-28