DFT Engineer
Beacon IndustriesJob Title
DFT Engineer
Role Summary
Experienced DFT Engineer to design and implement Design-for-Test solutions for ASIC/SoC products. The role is onsite in Santa Clara, CA and supports test architecture, silicon bring-up, fault analysis, and production test activities.
Experience Level
Mid-level — typically 5+ years of hands-on DFT experience.
Responsibilities
Primary responsibilities include designing DFT architecture, performing test analysis, and supporting silicon and production testing.
- Design and implement DFT architecture for ASIC and SoC designs.
- Develop and integrate Scan Compression, MBIST, LBIST, JTAG, and IJTAG solutions.
- Perform ATPG, fault simulation, and test coverage analysis.
- Support silicon bring-up, debug, characterization, and production test activities.
- Collaborate with Design, Verification, Physical Design, and Product Engineering teams across the development lifecycle.
Requirements
Must-have technical skills and tools; preferred items listed separately.
- Must-have: 5+ years hands-on Design-for-Test (DFT) experience.
- Must-have: Strong expertise in Scan, Scan Compression, MBIST, LBIST, ATPG, and JTAG.
- Must-have: Solid understanding of IEEE 1149.1, IEEE 1500, and IEEE 1687 (IJTAG) standards.
- Must-have: Experience with industry DFT tools such as Synopsys TestMAX / DFT Compiler, Siemens Tessent, or Cadence Modus.
- Must-have: Proficiency in Verilog and/or SystemVerilog.
- Must-have: Scripting experience (Python, Perl, Tcl, or Shell).
- Nice-to-have: ASIC/SoC development experience and background in silicon bring-up, debug, and production test.
- Nice-to-have: Strong problem-solving skills and ability to work effectively in cross-functional engineering teams.
Education Requirements
Not specified.
About the Company
Company: Beacon Industries
Technology/engineering company focused on analog and mixed-signal integrated circuit design and custom IC layout (SerDes, SRAM, high-speed interfaces), using Synopsys/Cadence EDA tools for design, simulation, verification, and silicon validation.
