DFT Engineer

Job Title

DFT Engineer

Role Summary

Work on Design-for-Test (DFT) architecture and implementation for complex ASIC/SoC products, focused on improving chip testability and manufacturing quality. The role interfaces with RTL, physical design, verification, and silicon bring-up teams.

Experience Level

Mid-level (3–12 years of experience preferred).

Responsibilities

Primary responsibilities implementing and validating DFT across the design flow.

• Design and implement DFT architectures for ASIC/SoC designs.
• Perform scan insertion, ATPG, MBIST, LBIST, and boundary-scan implementation.
• Run fault coverage analysis and generate test patterns.
• Integrate and validate compression and low-power DFT techniques.
• Collaborate with RTL, physical design, and verification teams; debug DFT issues in simulation and silicon bring-up.
• Support post-silicon validation and ensure test coverage and quality metrics for tapeout.

Requirements

Must-have technical skills and tools experience; preferred items listed separately.

• Strong understanding of DFT concepts and methodologies.
• Hands-on experience with scan, ATPG, JTAG, MBIST, and compression flows.
• Experience with industry DFT tools such as Tessent, SpyGlass DFT, Modus, or Tetramax.
• Proficient in Verilog/SystemVerilog and simulation/debug flows.
• Scripting skills in Tcl, Perl, or Python for automation and flow development.
• Familiarity with semiconductor design and test processes.

Nice-to-have:

• Experience with advanced process nodes and large SoC designs.
• Knowledge of low-power DFT techniques.
• Prior silicon debug and bring-up experience.
• Strong analytical skills and effective communication.

Education Requirements

Not specified.

About the Company

Company: CaritaTech

Engineering staffing and consulting firm providing placement and contract services for hardware, semiconductor, and embedded systems professionals, including roles in SoC/ASIC physical design and verification.