Job Title
DFT Engineer
Role Summary
Work on design-for-test (DFT) and ATPG for SoC/ASIC projects, focusing on test architecture, pattern generation, and debug. The role is part of the hardware/verification team supporting high-performance semiconductor programs.
Position is onsite in Santa Clara, CA, collaborating with RTL designers, validation, and manufacturing teams to deliver testable silicon.
Experience Level
Mid-level. Requires 5+ years of hands-on DFT/ATPG experience for SoC or ASIC designs.
Responsibilities
Primary responsibilities include implementing DFT solutions, generating and analyzing test patterns, and supporting test debug and validation.
- Design and implement scan-based DFT architectures and test insertion strategies.
- Develop and run ATPG pattern generation, analyze coverage and diagnose failures.
- Implement and validate MBIST memory test architectures and diagnostics.
- Define and execute IO test methodologies for interface and pin-level validation.
- Perform clock DFT verification and address clock-domain testability issues.
- Work with RTL and timing teams to ensure design testability and resolve issues.
- Use industry-standard DFT/ATPG EDA tools and debug test failures on silicon.
- Communicate technical status and contribute to project schedules in fast-paced programs.
Requirements
Must-have technical skills and experience.
- 5+ years hands-on experience in DFT and ATPG for SoC or ASIC designs.
- Strong understanding of DFT fundamentals including controllability and observability.
- Proven expertise in ATPG pattern generation, analysis, and debug.
- Experience with MBIST implementations and memory diagnostics.
- Knowledge of IO test methodologies and pin-level validation.
- Solid understanding of digital design and RTL fundamentals.
- Experience with industry-standard DFT/ATPG EDA tools.
- Strong analytical, problem-solving, and communication skills; able to work in fast-paced programs.
Education Requirements
Bachelor of Engineering (BE) is specified.
About the Company
Company: ITMC Systems

Date Posted: 2026-06-26