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DFT Engineer

Lumiere Systems
May 29, 2026
Full-time
On-site
Raleigh, North Carolina, United States
DFT Jobs, Level - Mid-Career

Job Title

DFT Engineer

Role Summary

Responsible for driving design-for-test (DFT) requirements and implementing DFT features and CAD flows to meet customer and manufacturing requirements. Works with design, CAD, and manufacturing teams to verify test coverage and debug silicon during bring-up.

Experience Level

Mid-level. Years of experience not specified.

Responsibilities

Primary responsibilities include implementing and validating DFT solutions across IP, block, and top levels and supporting hardware bring-up.

  • Translate and drive design requirements to meet customer specifications.
  • Pick up and run defined CAD tools and flows for assigned designs.
  • Analyze, debug, and implement DFT features using CAD tool flows.
  • Simulate and verify ATE test suites at IP, block, and top-level netlist.
  • Define and implement test strategy for complex mixed-signal designs.
  • Collaborate with global CAD and design teams to fix flows and improve features.
  • Provide debug and support to manufacturing test teams during hardware bring-up.
  • Develop specifications and design documentation related to DFT and test strategy.

Requirements

Must-have technical skills and competencies expected for the role.

  • Proven experience with DFT methodologies and implementing DFT features in ASIC/SoC designs.
  • Experience using CAD tools and established CAD flows for DFT and test development.
  • Ability to simulate and verify ATE test suites and work with netlist-level verification.
  • Experience defining test strategies for mixed-signal circuits and coordinating across design teams.
  • Strong debugging skills and experience supporting manufacturing test and silicon bring-up.
  • Clear communication and collaboration skills for cross-functional and global teams.

Education Requirements

Not specified.


About the Company

Company: Lumiere Systems

Engineering services firm specializing in semiconductor and ASIC design and verification for ARM-based SoCs. Engages in full verification lifecycle (UVM/SystemVerilog, formal, gate-level simulation) and collaborates with global verification teams and client partners.

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Date Posted: 2026-05-29