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DFT DV Verification Lead

Advanced Micro Devices
Full-time
On-site
Hyderabad, India
Level - Senior

Role Overview

The DFT DV Verification Lead is responsible for planning, building, and executing the verification of both new and existing features for AMD’s graphics processor IP. The aim is to ensure that the final design is devoid of bugs.

Position Expectations

The ideal candidate will possess a strong passion for modern processor architecture, digital design, and verification processes. You should be adept at collaborating with engineers across various locations and have excellent communication skills. Strong analytical and problem-solving skills are essential, along with a willingness to learn and tackle challenging issues.

Key Responsibilities

As a DFT DV Verification Lead, your main responsibilities include:

  • Utilizing verification methodologies such as OVM, UVM, or VMM.
  • Applying knowledge of Verilog and general logic design concepts.
  • Verifying DFT architectures, including Scan, ATPG, MBIST/LBIST, JTAG/Boundary Scan, and DFx features.
  • Developing and executing DFT verification plans, test scenarios, and coverage models.
  • Building SystemVerilog/UVM-based testbenches for DFT feature verification.
  • Verifying scan insertion, test modes, clock/reset handling, and test access mechanisms.
  • Validating MBIST/LBIST controllers and associated features.
  • Working closely with DFT implementation and ATPG teams to troubleshoot test failures.
  • Conducting gate-level simulations for DFT and test modes.
  • Analyzing functional/DFT coverage to ensure sign-off quality.
  • Supporting post-silicon debug and correlating with pre-silicon results.
  • Contributing to methodology improvements and best practices for DFT-DV.

Required Qualifications

The candidate should hold a BS/MS in Electrical Engineering, Computer Engineering, or Computer Science, along with a minimum of 8 years of design verification experience. Familiarity with OOP coding in SystemVerilog, SpecmanE, or C++, and experience with SystemVerilog Assertions are also required.

Education Requirements

BS or MS in Electrical Engineering (EE), Computer Engineering (CE), or Computer Science (CS).