DFT Architect

Job Title

DFT Architect

Role Summary

Senior technical authority responsible for defining and governing DFT architecture across Altera's FPGA, SoC, and multi-die platforms. The role owns end-to-end DFT strategy, drives methodology and tool adoption, and ensures testability, manufacturability, and silicon quality across large silicon programs.

Experience Level

Senior — requires extensive industry experience; the posting specifies 15+ years total industry experience and 10+ years in DFT architecture and related activities.

Responsibilities

Deliver architectural leadership, methodology, and governance for DFT across complex silicon programs.

• Define and drive long‑term DFT architecture for FPGA, SoC, processor, DSP, SERDES, IO, and multi‑die/chiplet products.
• Lead development of scalable DFT methodologies and RTL-to-GDS flows, including hierarchical and multi‑die integration.
• Architect scan, compression, ATPG, MBIST/LBIST, boundary scan, and in‑system test solutions to meet coverage and cost goals.
• Plan and integrate DFT for 2.5D/3D ICs, chiplets, and heterogeneous multi‑die systems.
• Collaborate with architecture, RTL, physical design, STA, validation, and product engineering teams for lifecycle integration.
• Establish and enforce DFT guidelines, test specifications, timing constraints, and sign‑off criteria.
• Lead root‑cause analysis for pre‑ and post‑silicon test failures, yield issues, and manufacturing escapes.
• Optimize production test strategies for coverage, test time, yield, and power‑aware testing.
• Drive adoption of next‑generation DFT technologies, automation, and EDA tool capabilities.
• Mentor DFT engineers and provide technical leadership across multiple programs.

Requirements

Must-have technical skills and experience.

• 15+ years industry experience (specified in posting).
• 10+ years architecting and implementing DFT solutions for complex SoC, FPGA, ASIC, or multi‑die designs.
• 10+ years experience in scan architecture, ATPG, compression, MBIST, LBIST, boundary scan, and hierarchical DFT.
• 10+ years experience with RTL‑to‑GDS DFT integration including scan insertion, STA constraints, low‑power DFT, and gate‑level verification.
• 10+ years experience with industry‑standard EDA tools for synthesis, scan insertion, ATPG, simulation/debug, formal verification, and STA.
• 10+ years supporting silicon bring‑up, manufacturing test flows, yield analysis, and failure debug.
• 10+ years developing DFT automation using scripting languages (Perl, Python, TCL).
• Proven ability to provide technical leadership and drive cross‑functional alignment across large engineering teams.
• Experience influencing EDA vendor tool strategy and deploying advanced DFT tool capabilities.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or related field is required; the posting specifies a Bachelor's with 15+ years of industry experience. A Master’s degree in Electrical Engineering, Computer Engineering, or related field is preferred.

About the Company

Company: Altera

Headquarters: Bengaluru, Karnataka, India

Altera provides leadership programmable solutions for applications ranging from cloud to edge, unveiling limitless AI possibilities. Their extensive product portfolio includes FPGAs, CPLDs, Intellectual Property, development tools, and System on Modules aimed at accelerating innovation in various fields.