Design Verification Senior Principal Engineer

Role Summary

The Design Verification Senior Principal Engineer at Marvell is responsible for leading the end-to-end SoC design verification (DV) execution and sign-off. This role involves collaborating with various teams to improve DV processes and ensuring high-quality execution of verification tasks.

Experience Level

Senior level with 18+ years of relevant experience.

Responsibilities

Key responsibilities include:

• Lead End-to-End SoC DV execution and sign-off.
• Define and drive improvements in DV processes.
• Collaborate with IP, Subsystem, and SoC teams on test plan creation.
• Work with design and DV teams for test plan development and execution.
• Coordinate with cross-functional teams for SoC-level DV execution.
• Support post-silicon validation and bring-up activities.
• Debug simulation failures and identify root causes.
• Architect and implement simulation testbenches using UVM & C.
• Develop and execute test plans to verify design correctness.

Requirements

Must-have skills and experience include:

• Master's/Bachelor’s degree with 18+ years of relevant experience.
• Experience leading technical teams and SOC/Subsys/IP level verification.
• Knowledge of ARM architecture and AMBA bus standards.
• Experience with interfaces such as DDR, HBM, PCIE, Ethernet, and USB.
• Proficient in UVM SOC/Subsys/block level testbenches programming.
• Experience with verification tools from Cadence, Synopsys, or Mentor.
• Proficient in scripting languages (tcl, Perl) and hardware emulation support.

Education Requirements

Master's or Bachelor's degree required.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.