Design Verification Engineer (Senior/Staff)

Role Summary

The Design Verification Engineer role is an opportunity to become an integral part of the R&D organization at Lattice Semiconductor, contributing to the development of innovative programmable logic solutions.

Experience Level

5+ years of relevant experience in Design Verification.

Responsibilities

• Develops and reviews test plan based on design specification.
• Creates constrained-random verification environments for complex designs (DUT).
• Implements coverage metrics using cover point and assertion.
• Creates and debugs tests for DUT.
• Resolves bugs with remote designers.

Requirements

• Strong understanding of verification process from test plan to coverage completion.
• Strong communication and analytical skills.
• Understanding of HDL (Verilog, SystemVerilog).
• Experience designing with FPGA is a plus.
• Proficiency in programming languages (C/C++, Perl, TCL, or Python).
• Familiarity with high-speed SERDES protocols (PCIe, Ethernet, CPRI or JESD204B/C, USB), memory technologies (DRAM, SRAM, Flash, DMA), interconnect protocols (AMBA AXI, AHB, APB) and peripherals (SPI, I2C or I3C) is advantageous.

Education Requirements

BS/MS/PhD in Electronics or Computer Engineering.

Minimum of 5 years experience with SystemVerilog/UVM.