Design Verification Engineer
BroadcomJob Title
Design Verification Engineer
Role Summary
The Design Verification Engineer will contribute to the functional verification of high-speed Ethernet PCS/MAC/Serdes subsystems and memory controllers. This role requires driving the verification lifecycle and collaborating with Design and Architecture teams.
Experience Level
Senior level with a requirement of 6-8 years of relevant industry experience.
Responsibilities
Key responsibilities include:
- Driving the full verification lifecycle including test planning, environment architecture, and final closure.
- Designing and implementing scalable, constrained-random UVM environments.
- Analyzing complex failures in Ethernet protocols and physical sublayers.
- Developing SystemVerilog Assertions and functional coverage models.
- Partnering with Design and Architecture teams on verification strategies.
Requirements
Mandatory technical skills include:
- Strong expertise in UVM and SystemVerilog.
- Experience with Ethernet design verification (10G through 800G+).
- Familiarity with SerDes integration and clock-domain crossing.
- Experience with High Bandwidth Memory or LPDDR controllers.
- Expertise in constrained-random verification and gate-level simulations.
Education Requirements
Bachelor’s Degree in Electrical/Computer Engineering or related field is required.
About the Company
Company: Broadcom
Headquarters: Irvine, California, United States
Broadcom is a global technology leader that designs, develops, and supplies a wide range of semiconductor and infrastructure software solutions. The company is known for its innovations in wireless and broadband communications, enabling a connected world.
