Design Verification Engineer

Role Summary

We are looking for an experienced Verification Engineer to join our team as a Technical Lead for cutting-edge server memory products. This individual will be responsible for driving the verification efforts of DDR interfaces, including advanced memory protocols such as DFI, DDR5, and LPDDR5, across a range of DIMMs (Dual In-line Memory Modules). The ideal candidate will possess expert-level knowledge of SystemVerilog, UVM, C/C++, and scripting languages like Python/Perl, along with a proven track record of multiple tape-out experiences and successful verification sign-offs in a high-performance server memory environment.

Experience Level

Level - Senior

Responsibilities

• Lead and guide a team of verification engineers in the development and execution of verification strategies for DDR5, LPDDR5, and DFI memory systems in server products.
• Comprehend the SOC as a complete system which includes HW (Silicon), FW, BIOS & SW and ensure alignment to enable all features of the memory interface.
• Work cross-functionally with IP/Domain architects to identify and assess complex technical issues/risks and develop architectural solutions.
• Support knowledge sharing and contribute to verification methodology.
• Responsible for architecture analysis and technical solutions for marketing/feature change requests.
• Collaborate closely with Design teams for Area and Floorplan refinement, Verification Test plan reviews, Timing targets, Emulation plans, Pre-Si bug resolution and Performance/Power Verification sign-offs.
• Support Post-Si teams for Product Performance, Power and functional issues debug/resolution.

Requirements

• Excellent communication and presentation skills.
• Developed and implemented SystemVerilog and UVM based testbenches, simulation environments, and functional coverage models for DDR5 and LPDDR5 systems.
• Experience in cross-functional collaboration to solve complex issues in memory systems, from firmware to hardware.
• Experience building VIPs and BFMs for memory interfaces preferred.
• Required simulation experience with GLS, NLP, XPROP.
• Proficiency in SystemVerilog assertions, constraints, and coverage.
• Working knowledge of formal verification methods and DFT flows preferred.

Education Requirements

Bachelor’s or Master’s degree in a related discipline preferred.