Design For Test Engineer

Role Summary

We are looking for a Design For Test Engineer to join our CPU Cores Team in Cambridge, UK. The candidate will have a strong technical background in DFT methodologies relevant to CPU core design and development. This role involves collaborating with various engineering teams to ensure first-pass silicon success.

Experience Level

This position is best suited for candidates with extensive experience in Design for Testability (DFT) and a robust work ethic, as well as strong leadership skills.

Responsibilities

• Stay updated on industry trends in the DFT domain and implement new DFT techniques in AMD products.
• Define and execute DFT architecture for next-generation multi-core microprocessors.
• Collaborate with architects, design, verification, and product engineering teams to integrate DFT requirements into the design process.
• Coordinate with DFT teams across different regions to develop unified strategies.
• Interface with DFT Tool Vendors to enhance testability.
• Develop efficient DFx flows compatible with design processes.
• Collaborate with testing and post-silicon debug teams to improve yield and troubleshoot silicon issues.
• Provide mentorship to junior engineers.

Requirements

The successful candidate should have experience in scan-based testing and industry-standard ATPG CAD tools, alongside strong knowledge of fault models, ATPG pattern verification, and use of EDA tools. Additionally, proficiency in scripting and debugging with Verilog, Python, or similar languages is critical. Familiarity with low-power design flows and post-silicon testing will be beneficial.

Education Requirements

Bachelor's, Master's, or PhD in Computer Engineering, Electrical Engineering, or Electronics Engineering.