Design for Test - DV Engineer

Role Summary

We are seeking an experienced Design for Test (DFT) Design Verification (DV) engineer to join our CPU Cores team in Cambridge, UK. This role involves working on AMD’s next-generation CPU core designs within a collaborative environment focused on technology innovation.

Experience Level

The ideal candidate should possess significant experience in DFT and DV methodologies, with a strong technical background in CPU core design and development.

Key Responsibilities

• Verify advanced Design for Test (DFT) functions such as Scan, Memory BIST, JTAG/IJTAG/P1500, and partitioned test structures.
• Collaborate with architects and designers to create detailed test plans for new features.
• Develop test benches and build directed and random verification tests to validate DFT implementation at RTL and gate-level.
• Debug test failures and work with engineers to resolve design issues.
• Improve code/functional coverage to meet design verification metrics across various milestones.
• Generate high-quality test patterns and contribute to test runs on silicon.
• Facilitate communication between test engineers and design teams in debugging silicon failures.
• Mentor and coach junior engineers while driving DFT DV strategies and improvements across the team.

Requirements

The candidate should display a passion for modern processor architectures, demonstrate excellent communication skills, and have a robust analytical mindset. Strong leadership qualities and a self-motivated work ethic are essential.

Education Requirements

Bachelor's or Master's degree in Computer, Electrical, or Electronics Engineering is required.