Design for Test (DFT) Engineer

Job Title

Design for Test (DFT) Engineer

Role Summary

Develop and implement testability solutions for complex digital ASICs, SoCs, and processors. Collaborate with design, verification, and test engineering teams to ensure products are designed for testability and that test issues are resolved throughout the development cycle.

Primary focus areas include DFT architecture and implementation, testability analysis, DFT verification, and test pattern generation.

Experience Level

Mid-level. Typically requires 5–7 years of relevant ASIC/DFT experience.

Responsibilities

Primary duties include designing and validating DFT features and contributing to system and chip-level designs.

• Design and implement DFT architecture and test logic for complex digital ASICs and SoCs.
• Perform testability analysis and fault modeling to evaluate test coverage and diagnostic quality.
• Develop and verify DFT methodology and generate test patterns.
• Simulate circuits at the transistor level and evaluate hardware feasibility of requirements and algorithms.
• Contribute to system-level design and optimize hardware for performance, power, and cost.
• Perform or guide physical layout tasks including floor-planning and parasitic-aware simulation.
• Document designs, capture requirements, and develop best practices; mentor less-experienced engineers.
• Collaborate with cross-functional teams to diagnose and resolve test-related issues throughout the product lifecycle.

Requirements

Must-have technical skills and working conditions.

• Proven proficiency in integrated circuit design and DFT (architecture, implementation, verification, test generation).
• Experience with transistor-level simulation and system-level hardware design.
• Ability to write detailed design specifications and technical documentation.
• Strong analytical, problem-solving, verbal and written communication, and organizational skills.
• Experience managing or leading small technical teams and prioritizing tasks to meet deadlines.
• Ability to obtain and maintain a U.S. government security clearance.

Education Requirements

Requires a Bachelor's degree in Engineering or a related field. Master's degree preferred. PhD acceptable. Employer-provided experience equivalencies: 5–7 years of experience with a Bachelor's degree, 3–5 years with a Master's degree, or 0–2 years with a PhD in ASIC hardware engineering or a related discipline.

About the Company

Company: Draper

Headquarters: Cambridge, MA, United States

Draper is an independent, nonprofit research and development organization based in Cambridge, Massachusetts. With over 2,000 employees, Draper develops advanced technologies in defense, space, biomedical engineering, and other national-security and commercial domains through multidisciplinary teams of engineers and scientists.