Design for Test (DFT) Engineer

Job Title

Design for Test (DFT) Engineer

Role Summary

Design and implement testability solutions for complex digital ASICs, SoCs, and advanced processors. Collaborate with design, verification, and test teams to ensure products are designed for testability and that test-related issues are resolved across the development cycle.

Experience Level

Mid-level. Typical experience expectations are in the mid-career range (approximately 3–7 years of relevant ASIC/DFT experience).

Responsibilities

Key responsibilities include designing and validating DFT solutions and supporting chip development from architecture through implementation.

• Define DFT architecture and implement scan, BIST, boundary-scan, and related test structures.
• Perform testability analysis and generate test patterns for digital ASICs and SoCs.
• Verify DFT logic and integrate with functional verification flows.
• Design and simulate circuits at the transistor level to meet architecture and requirement specifications.
• Contribute to system-level design and optimize hardware for performance, power, and cost.
• Perform or guide physical layout activities including floor-planning and parasitic-aware simulation.
• Drive solutions for ambiguous or evolving requirements and document design decisions.
• Mentor junior engineers and develop best-practice documentation; contribute to proposals and business development as needed.

Requirements

Essential technical skills, professional abilities, and other mandatory conditions.

• Proven experience implementing DFT for digital ASICs/SoCs (architecture, implementation, and verification).
• Experience with test pattern generation and DFT verification flows.
• Transistor-level circuit design and simulation experience; familiarity with parasitic-aware simulation.
• Understanding of integrated circuits, semiconductors, and computer architecture.
• Ability to write detailed design specifications and clear technical documentation.
• Experience leading or managing small technical teams and coordinating cross-functional work.
• Strong analytical, problem-solving, organizational, and time-management skills; effective verbal and written communication.
• Ability to prioritize tasks and meet deadlines in a multidisciplinary environment.
• Must be able to obtain and maintain a U.S. government security clearance (required for selected applicants).

Education Requirements

Requires a bachelor’s degree in Engineering or a related field; a master’s degree is preferred. Experience mapping provided by the employer: 5–7 years with a bachelor’s degree, 3–5 years with a master’s degree, or 0–2 years with a PhD in ASIC hardware engineering or a related discipline.

About the Company

Company: Draper

Headquarters: Cambridge, MA, United States

Draper is an independent, nonprofit research and development organization based in Cambridge, Massachusetts. With over 2,000 employees, Draper develops advanced technologies in defense, space, biomedical engineering, and other national-security and commercial domains through multidisciplinary teams of engineers and scientists.