Design Engineering Architect

Role Overview

The Design Engineering Architect role is a senior technical leadership position focused on defining the verification infrastructure for next-generation Tensilica advanced CPU cores and configurable processors. This role requires establishing methodologies that ensure the functional integrity of complex instruction set architectures (ISA).

Experience Level

The ideal candidate should possess a deep understanding of SoC/CPU/DSP verification with at least 10 years of relevant experience.

Responsibilities

• Methodology Strategy: Define and oversee the long-term DV architecture to ensure scalability across different processor variants and generations.
• Verification Infrastructure: Lead the development of simulation testbenches utilizing C/C++/RTL and create reusable UVM environments.
• Advanced Verification: Integrate formal verification methods along with AI-driven coverage analysis.
• Cross-Functional Collaboration: Work closely with microarchitecture, RTL design, and software teams to align verification plans with ISA requirements.
• Mentorship: Provide guidance and technical direction, establishing high standards for quality verification metrics across global teams.

Requirements

• B.Tech/M.Tech in Electronics and Communication Engineering (ECE).
• Over 10 years of experience in SoC/CPU/DSP verification.
• Deep expertise in SystemVerilog/UVM and C/C++ for architectural modeling.
• Experience with processor integration, particularly RISC-V or ARM, and protocols like AMBA/PCIe.
• Proficiency in scripting languages such as Perl, Python, or Tcl for automation of verification workflows.
• A proven record in verifying complex systems including pipelines and memory subsystems.

Education Requirements

BE/BTech/ME/MTech/MS in a relevant field.