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Design Engineer Lead

Lattice Semiconductor
Full-time
On-site
San Jose, CA
$175,000 - $219,000 USD yearly
Level - Senior

Role Summary

As a Design Engineer Lead, you will be responsible for overseeing hardware IP and integration design projects, guiding a cross-functional team through the entire process from concept to production.

Experience Level

20 years of substantial experience in hardware design and integration.

Responsibilities

  • Lead a team of engineers across multiple geographical locations.
  • Guide multiple programs from concept to tape out and production release.
  • Utilize expertise in System Verilog, Synthesis, and Static Timing Analysis.
  • Apply DFx methodology at both the IP and chip level.
  • Debug complex issues related to design, including floor-planning and timing closure.
  • Engage deeply with leading IP vendors to drive the IP roadmap and conduct competitive analysis.
  • Stay current with the latest advancements in technology and design methodologies.

Requirements

  • Proficiency in programming (C/C++, Perl, TCL, or Python).
  • Strong communication skills with experience presenting to executive leadership.
  • Ability to debug system-level use cases through verification and emulation.
  • Familiarity with high-speed interface technologies like LPDDR5 and USB4.0.
  • Experience with system interconnects and processor architecture (e.g., ARM, RISC-V).

Education Requirements

Not specified, but extensive experience in related design fields is expected.