Design Engineer II

Job Title

Design Engineer II

Role Summary

Responsible for verification of digital RTL and development of reusable verification components and environments for high-performance physical IP targeting industry-standard protocols. Works within a small, focused IP design/verification team and collaborates with design, verification, and project management across multiple geographies.

Position is full-time and expected to be based in the Montreal, QC office; occasional travel (~5% or less) may be required.

Experience Level

Mid-level (Design Engineer II). Specific years of experience not stated.

Responsibilities

Key responsibilities include designing and executing verification activities and contributing to verification infrastructure and flows.

• Verify digital RTL and ensure functional and code coverage closure.
• Develop reusable verification components, environments, and testbenches.
• Create and execute test plans and metric-driven verification strategies.
• Develop functional coverage models and checkers; analyze coverage gaps.
• Contribute to verification flow and infrastructure development, including scripting and automation.
• Collaborate with digital and analog design teams, project management, and cross-site engineers to report progress and resolve issues.
• Participate in reviews and debugging sessions to track verification status and quality metrics.

Requirements

Must-have and preferred technical skills for this role.

Must-have:

• Understanding of verification architecture and methodologies, including metric-driven verification.
• Familiarity with Universal Verification Methodology (UVM) concepts.
• Knowledge of SystemVerilog Assertions (SVAs) and basic digital design flow.
• Experience defining and implementing functional coverage and checks.
• Strong problem solving and communication skills; ability to work independently and within a small team.

Nice-to-have:

• Experience coding in SystemVerilog UVM.
• Experience with scripting languages such as Python, Perl, Ruby, sed, or awk for testbench automation.
• Familiarity with standard protocols (PCIe, USB, SATA, Ethernet, DisplayPort, HDMI).
• Exposure to formal verification, mixed-signal design, Cadence tools, or low-power verification (CPF/UPF).

Education Requirements

Required: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field. Preferred: Master of Science in EE/CPE/CS or related field. (Education in related technical disciplines noted; no certifications specified.)

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.