Design Engineer II

Job Title

Design Engineer II

Role Summary

Lead and execute post-silicon characterization and validation of analog and digital IP-based silicon solutions. Work with a small team to run lab tests, develop compliance and interoperability test suites, and deliver measured results to R&D and product teams.

Experience Level

Mid-level — typically 2–5 years of relevant post-silicon PHY, systems interoperability, and compliance testing experience.

Responsibilities

Primary responsibilities include hands-on silicon validation, lab test development, and team coordination:

• Plan, execute, and document electrical and protocol interoperability and compliance tests for high-speed interfaces.
• Operate and apply lab equipment for debug and validation (oscilloscopes, BER testers, protocol exercisers/analyzers).
• Develop lab automation, test scripts, and analysis workflows to debug and root-cause silicon failures.
• Design and review PCB schematic and layout for high-speed interfaces; perform signal and power integrity checks and fixes.
• Develop and run reliability qualification tests (ESD, Latchup, HTOL) to meet industry standards.
• Isolate PHY and controller (MAC/PCS) features to define test scope and calibrations.
• Mentor and provide day-to-day guidance to a small team of engineers; coordinate with remote R&D and marketing teams.

Requirements

Must-have technical skills and experience. Nice-to-have items are listed separately.

• Must-have: Experience in post-silicon PHY, systems interoperability, and compliance testing.
• Must-have: Physical-layer and protocol-layer experience on at least one high-speed SERDES (Ethernet, PCIe, CXL, UCIe).
• Must-have: Proven ability to interpret Ethernet/PCIe/UCIe specifications and translate them into electrical and protocol test suites.
• Must-have: Hands-on debug skills with oscilloscopes, bit error rate testers, protocol exercisers, and protocol analyzers.
• Must-have: Experience developing lab automation and test-result analysis scripts (Python, C/C++).
• Must-have: Strong Verilog RTL skills for FPGA-based validation.
• Must-have: Experience designing PCBs at schematic and layout level for high-speed interfaces and performing signal/power integrity analysis.
• Must-have: Experience leading or mentoring a small team (2–3 years of management/mentoring experience preferred).
• Nice-to-have: Familiarity with PCIe/UCIe LTSSM states, UCIe interfaces, and additional Ethernet/CXL experience.

Education Requirements

BTech or MTech mentioned: typical guidance was 2–5 years with a BTech or 4 years with an MTech; equivalent relevant practical experience is accepted.

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.