Design Engineer II

Job Title

Design Engineer II

Role Summary

Experienced analog/mixed-signal design engineer responsible for architecting and delivering high-speed interface IPs for die-to-die/chiplet systems, with emphasis on UCIe-based D2D links and advanced packaging. The role owns designs from architecture through silicon bring-up and works cross-functionally with layout, verification, package, and system teams.

Experience Level

Mid-level — the posting requests 5+ years of hands-on analog / mixed-signal IC design experience.

Responsibilities

Primary responsibilities focus on analog design, integration, and validation of high-speed D2D interfaces and related circuits.

• Architect, design, and deliver high-speed analog/mixed-signal circuits for Die-to-Die and chiplet systems (UCIe-compliant interfaces).
• Own analog blocks for clocking, TX/RX front-ends, termination, biasing, and equalization support circuits.
• Perform schematic design, simulation, optimization, and trade-off analysis across PVT corners using EDA tools.
• Drive architecture definition and feasibility studies considering signal integrity, power, noise, and package parasitics.
• Collaborate with advanced packaging (2.5D/3D, interposers, organic substrates) to co-optimize circuit and package design.
• Support layout reviews, parasitic extraction analysis, and post-layout sign-off for high-speed performance.
• Work with AMS verification, digital, and system teams for full-chip integration and validation.
• Participate in silicon bring-up, post-silicon debug, characterization, and correlation with simulations.
• Contribute to design methodology, checklists, and best practices for high-speed analog and D2D designs.

Requirements

Key technical and professional requirements. Degree information is summarized under Education Requirements below.

• Must-have: 5+ years hands-on analog/mixed-signal IC design experience.
• Must-have: Strong experience with high-speed interface design (e.g., DDR, PCIe, SerDes, Die-to-Die links).
• Must-have: Solid understanding of UCIe concepts, D2D PHY requirements, and chiplet architectures.
• Must-have: Experience with advanced packaging technologies and package-induced effects on high-speed signaling.
• Must-have: Proficiency in schematic-level design, simulation, and debug across PVT corners.
• Must-have: Strong fundamentals in analog circuit theory, signal integrity, noise analysis, and clocking.

Nice-to-have:

• Direct hands-on experience with UCIe PHY design or integration.
• Exposure to AMS verification flows and mixed-signal simulation environments.
• Experience with post-silicon debug and correlation.
• Knowledge of power integrity, thermal considerations, and package-aware design flows.
• Ability to mentor junior engineers and lead technical discussions.

Education Requirements

Bachelor’s or Master’s degree in Electrical/Electronics Engineering or a related technical field (as stated). The posting specifies degree-level expectations rather than an explicit equivalent-experience clause.

Company Note

Cadence is an electronic design automation company focused on software, hardware, and IP for advanced semiconductor design. Cadence is an equal opportunity employer.

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.