Debug/Trace/Profiling Design Engineer

Job Title

Debug/Trace/Profiling Design Engineer

Role Summary

Design and deliver debug, trace and profiling IP for RISC-V processor subsystems. Work on configurable RTL generator development using Chisel/FIRRTL, collaborate with architecture, verification, software and performance teams, and engage with customers and tools vendors to define and productize debug/trace solutions.

Experience Level

Senior — requires 7+ years of industry experience leading and contributing to architecture, microarchitecture and RTL design for debug/trace/profiling hardware for high-performance processors.

Responsibilities

Deliver production-quality debug, trace and profiling hardware and integrate it into SiFive's processor IP toolchain.

• Architect, design and implement debug, trace and profiling hardware modules and subsystems.
• Collaborate with architecture, performance, software and hardware teams on exploration and specification.
• Implement RTL generators with extensive self-configuration and configurability.
• Integrate designs into the Chisel/FIRRTL framework and contribute improvements to generation, documentation, verification, and packaging flows.
• Perform initial sandbox verification and coordinate with design verification to develop and execute verification plans.
• Create and maintain clear documentation and participate in collaborative design reviews.

Requirements

Must-haves and technical expectations.

• Deep knowledge of debug, trace and profiling architecture and concepts.
• Familiarity with debug interfaces such as JTAG and cJTAG.
• Strong understanding of CPU architectures, power management and SoC design.
• Experience with debugging tools and profiling methods.
• Proficiency in hardware RTL design using Verilog, SystemVerilog, or VHDL.
• 7+ years of industry experience leading and directly contributing to relevant architecture, microarchitecture and RTL design.
• Attention to detail, focus on high-quality design, and effective teamwork skills.
• Knowledge of at least one object-oriented and/or functional programming language.

Nice-to-have:

• Experience with Chisel/Scala and the RISC-V architecture.
• Familiarity with Git, Jira and Confluence.

Education Requirements

MS or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline (as stated in the posting).

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.