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Customer Engagement Engineer II

Cadence Design Systems
September 25, 2026
Full-time
On-site
San Jose, California, United States
$105,000 - $195,000 USD yearly
EDA Jobs, Level - Mid-Career

Job Title

Customer Engagement Engineer II

Role Summary

As a member of the HSV Customer Support Team, you will provide technical support for Palladium, Protium and Virtual Protocol (PDAPP) products, working with customers, field account engineers, and R&D to diagnose and resolve issues. The role focuses on reproducing customer problems, validating fixes, and tracking quality metrics.

Experience Level

Mid-level. Typically requires a minimum of 1 year of experience in digital design and/or verification or in applications engineering/technical support.

Responsibilities

Primary responsibilities include handling customer cases, coordinating with R&D and field teams, and validating fixes.

  • Respond to incoming customer and field AE cases reported in SFDC.
  • Reproduce customer issues and create testcases to isolate problems.
  • Report bugs to R&D and collect required collateral and testcases.
  • Test and validate R&D fixes and patches.
  • Track customer metrics in JIRA and generate quality reports for management.
  • Collaborate with field AEs and customers to resolve escalated technical issues.

Requirements

Must-have technical skills and experience; preferred items noted.

  • Minimum 1 year experience in design/verification of complex digital designs or in applications engineering/technical support.
  • Strong understanding of logic design and design debug techniques.
  • Proficiency in HDLs: Verilog, SystemVerilog, and VHDL.
  • Proficiency with Unix/Linux scripting (ksh/bash/csh).
  • Ability to create testcases and reproduce customer issues quickly.
  • Excellent written and verbal communication skills; able to explain complex issues clearly to internal teams and customers.
  • Familiarity with verification methodologies and EDA environments.
  • Nice to have: experience with emulation (Cadence Palladium), SVA, SystemVerilog coverage, UPF (low power), UVM.
  • Nice to have: familiarity with PCIe, USB, and Ethernet protocols.
  • Nice to have: experience using JIRA and Salesforce (SFDC) for tracking cases.

Education Requirements

Requires a Bachelor’s degree in Electrical Engineering (EE) or Computer Engineering (CE). A Master’s degree in EE/CE is preferred. The posting specifies a minimum of 1 year of relevant experience.


About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.

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Date Posted: 2026-09-23