Custom SOC IP Verification Engineer

Job Title

Custom SOC IP Verification Engineer

Role Summary

Verify fabric and interconnect IP and full-chip integration for advanced custom SoC designs. The role focuses on developing verification plans and UVM/SystemVerilog testbenches to ensure correctness, performance, and protocol compliance of on-chip fabrics and interconnect subsystems.

This position works closely with architecture, design, software/firmware, modeling, emulation, and post-silicon teams to deliver first-time-right silicon.

Experience Level

Mid-level — typically requires around 5+ years of ASIC verification experience with emphasis on fabric/interconnect or NoC verification.

Responsibilities

Primary responsibilities include IP- and system-level verification of interconnect fabrics and ensuring robust integration at full-chip scale.

• Verify fabric and interconnect IP blocks and full-chip integration, covering DMA, routing, arbitration, ordering, flow control, and protocol compliance.
• Develop and execute test plans for IP-level and system-level interconnect verification using UVM-based environments.
• Design and implement constrained-random and directed SystemVerilog testbenches for NoC topologies and multi-agent SoC scenarios.
• Collaborate with Architecture, SW/FW, Design, Modeling, Emulation, and Post-Silicon Validation teams to align verification strategy and execution.
• Drive development of silicon and platform verification strategies and methodologies for fabric and interconnect subsystems.

Requirements

Must-have technical skills and experience required for successful execution of the role.

• 5+ years of ASIC verification experience focused on fabric, interconnect, or NoC verification at IP and full-chip levels.
• Strong proficiency in SystemVerilog and UVM methodology.
• Hands-on experience with interconnect and bus protocols (for example AMBA AXI, CHI, or equivalent) and understanding of ordering, coherency, and flow-control semantics.
• Familiarity with SoC architectures, NoC topologies, and multi-initiator/multi-target interconnect designs.
• Proficiency in scripting languages such as Python, Perl, or TCL.

Nice-to-have:

• Performance verification and bandwidth/latency analysis for interconnect fabrics.
• Experience with verification IP for bus protocols and emulation platforms (e.g., Palladium, Veloce) for full-chip validation.
• Experience with GPU or AI accelerator SoC interconnects.
• Experience with formal verification or assertion-based verification (SVA) applied to fabric and protocol properties.

Education Requirements

B.S. or M.S. in Computer Engineering, Electrical Engineering, or a related technical field — or equivalent practical experience.

About the Company

Company: NVIDIA

Headquarters: Santa Clara, California, USA

NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.