Role Summary
This role involves proposing and developing advanced layout design techniques within a global team focused on semiconductor innovation.
Experience Level
Mid-level, with over five years of relevant experience.
Responsibilities
The main responsibilities include:
- Proposing and developing layout design techniques and methodologies using Tcl/Perl/Python.
- Running verification on existing designs and minimizing rework through innovative scripts.
- Collaborating across global teams to optimize the design environment.
- Driving the adoption of new methodologies by training global design teams.
- Maintaining and improving workflow automation for high productivity in custom analog layout.
Requirements
Must-have skills include:
- BS/MS in Electrical Engineering, Computer Engineering, or related field.
- Expertise in custom analog layout design, particularly with sub-5nm FinFet/Gate-All-Around nodes.
- Proficiency in scripting languages: Tcl, Perl, and Python.
- Ability to debug LVS and DRC reports.
- Basic understanding of circuit design and digital synthesis workflows.
Education Requirements
BS/MS in Electrical Engineering, Computer Engineering, or a related field.
About the Company
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.

Date Posted: 2026-04-20