CPU Physical Design Engineer

Job Title

CPU Physical Design Engineer

Role Summary

Implement and optimize the physical design of high-performance CPUs from RTL to a manufacturable layout. Work on floorplanning, synthesis, place-and-route, timing closure, power distribution, and signoff to meet performance, power, area, and manufacturability targets.

Collaborate across architecture, logic, circuit, verification, design automation, and EDA partners to deliver tape-out-ready CPU designs using advanced process technologies.

Experience Level

Mid-level: typically requires multiple years of relevant physical design experience (commonly 3+ years of industry experience for entry with a Bachelor's; experience expectations vary by degree and role).

Responsibilities

Key responsibilities include:

• Implement CPU physical designs from RTL through a design database ready for manufacturing.
• Execute and optimize the full backend physical design flow: floorplanning, synthesis, place-and-route, clock tree synthesis, static timing analysis, and layout verification.
• Perform verification and signoff activities such as formal equivalence checks, reliability and layout verification, and structural design rule checks.
• Analyze design results to identify improvements in power, performance, area, timing, and overall design quality.
• Collaborate with architecture, logic, circuit, and design automation teams to resolve complex integration and implementation issues.
• Develop and enhance physical design methodologies, flows, and automation scripts.
• Work with internal teams and EDA partners to evaluate and improve tools and capabilities, and apply lessons learned to future products.

Requirements

Must-have skills and experience (minimums for initial consideration):

• Hands-on physical design implementation experience using industry-standard EDA tools (for example Synopsys Fusion Compiler, Cadence Genus/Innovus, or equivalent).
• Practical experience across backend workflows: floorplanning, place-and-route, clock tree synthesis, static timing analysis, and layout verification.
• Scripting for automation and analysis using TCL, Perl, Python, or similar languages.
• Familiarity with RTL-to-GDS physical design flows and associated signoff activities.
• Ability to analyze timing, power, and area results and drive optimization actions.

Preferred / nice-to-have:

• Experience with CPU, SoC, or other complex high-performance designs and tape-out using advanced process nodes.
• Low-power design experience (multiple power domains, UPF, power analysis) and timing/power optimization techniques.
• Experience automating RTL-to-GDS flows and applying AI/ML methods to place-and-route or physical optimization.
• Experience collaborating with EDA vendors or working across multiple EDA tool flows.
• Understanding of thermal or power-reduction techniques relevant to CPU designs.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field with 3+ years of relevant experience; OR a Master's degree in a related field with 1+ year of experience. A PhD in a related field with some practical experience is listed as preferred. Qualifications may also be met via a combination of work experience, internships, or relevant coursework.

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.