CPU Design Verification Architect

Role Summary

We are looking for a highly skilled CPU Design Verification Architect to lead unit-level verification for complex CPU designs. This role requires ownership of comprehensive test plans, driving coverage closure, and close collaboration with RTL designers to ensure tape-out readiness. You will also support emulation and post-silicon validation efforts while mentoring junior engineers.

Experience Level

Applicants should possess a minimum of 16 years experience in CPU verification, with a strong focus on module-level design verification.

Responsibilities

• Architect and implement unit-level verification environments using C++/SystemVerilog/UVM.
• Develop detailed test plans for functional and performance verification specifically for Load/Store, Scheduler, and Execute Units.
• Create directed and random stimulus, checkers, and coverage models.
• Debug simulation failures and work closely with RTL designers to resolve issues.
• Drive coverage closure to ensure high-quality tape-out readiness.
• Support emulation and post-silicon validation tasks.
• Mentor junior engineers and contribute to establishing verification best practices.

Requirements

• Strong understanding of out-of-order execution, memory ordering, and cache coherence.
• Proficiency in SystemVerilog, UVM, C++, and Python.
• Experience with x86, ARM, or RISC-V architectures.
• Familiarity with simulation tools (VCS, Verilator), waveform debugging, and scripting.
• Excellent problem-solving and communication skills.

Education Requirements

A bachelor's degree in Electrical Engineering, Computer Engineering, or a related field is typically expected for a senior-level verification engineer position.