Chip Lead / Physical Design Director

Job Title

Chip Lead / Physical Design Director

Role Summary

Lead physical-design architecture and execution for advanced system-on-chip (SoC) projects, guiding teams from RTL/Netlist to GDS. The role interfaces directly with customers and internal R&D to deliver against aggressive performance, power, area, and schedule (PPAS) targets for markets such as data center, automotive, and AI.

Experience Level

Senior — 15+ years of industry experience in Physical Design.

Responsibilities

Responsible for technical leadership, customer engagement, and delivery of full-chip physical implementation services.

• Serve as technical lead for Physical Design and DFT teams on complex customer SoC projects from RTL/Netlist to GDS.
• Own technical decisions, design trade-offs, and problem solving to meet PPA and schedule targets through delivery.
• Advise customers on foundry/node, standard-cell libraries, memory compilers, and sign-off criteria to balance features and cost.
• Collaborate with internal teams to present technical plans, report status, and promote methodology or AI-driven improvements.
• Coordinate with RTL/synthesis teams to ensure front-end metrics are achieved prior to physical execution gates.
• Partner with Cadence tools R&D to improve tools and flows to meet customer needs.
• Document and share best practices and lessons learned to improve efficiency and project success rates.

Requirements

Must-have technical skills and experience required to perform the role.

• 15+ years of experience in Physical Design (industry experience).
• Strong knowledge of digital design fundamentals, semiconductor fundamentals, and static timing analysis (including constraints).
• Experience with IC digital implementation flows and backend EDA tools: place & route, clock tree synthesis, IR drop analysis, timing and power closure.
• Proven track record of complete top-level chip design closure and PPA optimization under aggressive constraints.
• Experience with advanced process nodes (7 nm and below).
• Proficiency in scripting (Tcl, Perl, or Python).
• Strong customer-facing communication, problem-solving skills, and ability to build technical relationships across RTL, DFT, CAD, and library teams.

Nice-to-have:

• Experience with front-end EDA tools (synthesis, DFT, logical equivalence checking) and prior work with tools such as Genus, Innovus, Conformal, Tempus, Modus, Voltus or equivalent.
• Experience with advanced nodes at 5 nm and below.
• Domain expertise in CPUs, GPUs, AI engines, NoCs, or high-speed interfaces.
• Experience with 3D IC design.

Education Requirements

Bachelor's degree in Computer Science, Computer Engineering, Electrical Engineering, or a related field required. Master's degree in those fields is preferred.

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.