Cache DFT Verification Engineer

Role Summary

You will leverage your technical skills to aid in the verification of AMD's upcoming CPU microprocessors. This role involves maintaining and enhancing existing verification test benches for cache functionalities, including Design for Test (DFT) features like Memory Built-In Self-Test (MBIST). You will engage in various projects to meet the team's goals by writing and executing comprehensive test plans, developing high-quality solutions, and collaborating with cross-functional teams.

Experience Level

This position requires the ability to work collaboratively in a team environment with architects and RTL designers. The ideal candidate should possess strong communication skills, demonstrate ownership, and exercise initiative while managing time effectively. Previous experience with microprocessor or ASIC design verification is preferred.

Responsibilities

- Perform functional and DFT feature verification of high-speed microprocessor designs, including infrastructure development and test suites at behavioral RTL and gate levels.
- Develop environments and test plans for comprehensive verification and debugging.
- Engage in formal verification techniques development.
- Establish an automated regression infrastructure for functional verification.
- Collaborate with engineers to verify DFT microarchitecture for AMD CPUs.
- Work with product test teams during product test phases.
- Develop, run, and debug tests using x86 assembly and other languages to validate microprocessor functionality.
- Handle simulation discrepancies and ensure project quality objectives are met through coverage measurement and analysis.
- Create infrastructure for post-silicon validation pattern generation and provide debug expertise for post-silicon issues.
- Coordinate with cross-functional teams on project deliverables and manage dependencies effectively.

Requirements

- Prior verification experience with microprocessors/ASIC designs is highly desired.
- Proficiency in Verilog HDL and strong programming skills in C/C++, x86 assembly, Perl, and Ruby.
- Robust understanding of computer architecture, DFT features including JTAG protocols, built-in self-test designs, and fault simulation techniques.
- Familiarity with deep sub-micron design principles and memory fault models is beneficial.
- Knowledge of formal verification tools and techniques is a plus.

Education Requirements

A Bachelor's, Master's, or PhD in Electrical Engineering or Computer Engineering is preferred.