ATE Test Engineering Architect
Lead development and deployment of production ATE test solutions for large complex SoCs used in Cadence Emulation Products. Own ATE test strategy and execution from first-silicon bring-up through qualification and high-volume manufacturing, partnering with design, DFT, OSATs, and test houses.
Hands-on technical leadership focused on silicon quality, yield, and scalable test solutions.
Senior — requires extensive industry experience; see Education Requirements for degree and years guidance.
Primary responsibilities include development, deployment, and production support of ATE test programs.
Must-have technical skills and proven production experience.
BS with a minimum of 12 years of relevant experience, or MS with a minimum of 10 years, or PhD with a minimum of 8 years.
California annual salary range: $178,500 to $331,500. May be eligible for incentive compensation (bonus, equity) and benefits.
Apply: Cadence careers — apply
For accommodation requests: staffing@cadence.com
Company: Cadence Design Systems
Headquarters: San Jose, California, USA
Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.
