ATE Test Engineer Junior

Job Title

ATE Test Engineer Junior

Role Summary

Join the semiconductor test engineering team in Valbonne (Sophia Antipolis) to develop, validate, and optimize automated test equipment (ATE) solutions for wafer sort and final test of semiconductor devices and IP.

Collaborate with design, product, and validation teams across France, India, and the United States to support silicon bring-up, production ramp-up, and customer qualification.

Experience Level

Entry-level / Junior — 0–3 years of professional experience.

Responsibilities

Primary responsibilities include developing ATE test programs, executing device characterization, and supporting production and customer qualification.

• Develop, debug, and maintain ATE test programs for wafer sort and final test.
• Convert design test patterns (VCD, WGL, STIL) into ATE-compatible formats and implement functional, parametric, and characterization tests.
• Define test strategy, coverage, and limits aligned with design specifications.
• Perform silicon bring-up, characterization, shmoo analysis, and debug campaigns.
• Collect, process, and analyze ATE data using scripts and tools to identify failures and trends.
• Collaborate with design, IP, and product teams to debug failing devices and resolve issues.
• Contribute to test methodologies, loadboard and hardware interface development, and optimize test time, cost, and quality.
• Use lab equipment (oscilloscopes, curve tracers) for validation and debug; support production ramp and customer qualification.

Requirements

Must-have technical skills and professional attributes.

• Knowledge of semiconductor device testing and characterization methodologies.
• Programming experience in C, C++, Python, or Java for test development and data processing.
• Data analysis, troubleshooting, and debugging skills.
• Familiarity with digital electronics and semiconductor fundamentals.
• Ability to work effectively in multicultural, cross-functional teams and communicate in English.

Preferred (nice-to-have):

• Experience with ATE platforms (e.g., Advantest 93K, Teradyne).
• Basic knowledge of DFT and functional test methodologies or hardware design (loadboards, packages).
• Familiarity with semiconductor manufacturing processes and memory/mixed-signal testing (CMOS, DRAM, SRAM).

Education Requirements

Master's degree in Electrical Engineering, Microelectronics, Electronics, Computer Engineering, or a related technical discipline. The position targets junior engineers with 0–3 years of experience.

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.