ASIC Verification - Senior Engineer

Job Title

ASIC Verification - Senior Engineer

Role Summary

Senior verification engineer responsible for specifying, architecting, implementing, and executing verification environments and test plans for DesignWare IP cores. The role is part of the DesignWare IP Verification R&D team and works closely with RTL designers and global verification teams to drive verification closure.

Primary mission: ensure delivery of robust, high-quality IP through coverage-driven verification, regression management, and automation.

Experience Level

Senior — typically 3+ years of professional ASIC/IP verification experience (see Education Requirements for degree-specific guidance).

Responsibilities

Accountabilities for the role include designing verification environments, executing tests, and improving verification practices.

• Specify, architect, implement, and maintain SystemVerilog-based verification environments and testbenches for IP cores.
• Develop and execute unit- and system-level test plans and regression suites.
• Design, code, and debug test cases, assertions, and functional coverage models; perform coverage analysis.
• Manage regression testing to meet quality metrics and verification closure targets.
• Collaborate with RTL designers and global verification teams to identify and resolve issues.
• Automate verification flows and tooling using scripting (Perl, TCL, Python).
• Contribute to verification methodology improvements, VIP development, and formal verification efforts.
• Mentor junior engineers and share best practices across multi-site teams.

Requirements

Key skills and experience required and desirable for successful performance in this role.

• Must-have: Strong SystemVerilog HVL testbench development and hands-on experience with UVM/OVM/VMM methodologies.
• Must-have: Practical experience with industry-standard simulators and debugging tools (examples: VCS, NC, MTI).
• Must-have: Experience developing functional coverage models and driving coverage-driven verification.
• Must-have: Proficiency in scripting for automation (Perl, TCL, Python) and familiarity with Verilog.
• Must-have: Working knowledge of common interfaces/protocols such as MIPI-I3C, UFS/Unipro, AMBA, SD/eMMC, Ethernet, DDR, PCIe, USB.
• Nice-to-have: Experience with VIP development, formal verification techniques, and multi-site/global team collaboration.
• Nice-to-have: Demonstrated ability to define and meet quality metric goals and improve verification efficiency.

Education Requirements

Requires a BSEE with 3+ years of relevant ASIC/IP verification experience, or an MSEE with 1+ years of relevant experience. Field: Electrical/Electronics Engineering (or closely related technical discipline).

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.