ASIC Verification Principal Engineer

Role Summary

An experienced and highly skilled ASIC Digital Verification Engineer with a passion for ensuring the highest quality in digital design. You have a deep understanding of verification methodologies and are proficient in using advanced verification tools and techniques. Your expertise allows you to work independently, taking on complex challenges and delivering innovative solutions.

Experience Level

Level - Senior

Responsibilities

• Designing, implementing, and optimizing verification environments to ensure the correctness of Interface IP protocols.
• Creating, executing and tracking against detailed test plans to verify complex ASIC designs.
• Developing and maintaining verification IP and testbenches using System Verilog and UVM.
• Collaborating with design and architecture teams to identify and fix bugs.
• Performing functional coverage analysis and driving coverage closure.
• Mentoring and guiding junior verification engineers in best practices and methodologies.

Requirements

• Extensive experience in ASIC digital verification, specifically with Interface IP protocols, such as PCIe, CXL, DDR, Ethernet, AMBA (CHI, AXI, AHB, APB).
• Proficiency in System Verilog, SVA and UVM methodologies.
• Strong understanding of digital design and verification concepts.
• Familiarity with wider digital ASIC and IP development flow, including RTL design through synthesis.
• Experience with simulation tools such as VCS, Model Sim, or similar.
• Strong analytical and problem-solving skills, with the ability to tackle complex and unique design challenges.
• Excellent communication skills, with the ability to effectively collaborate with cross-functional teams and stakeholders.

Education Requirements

Not specified.