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ASIC Verification Engineer

Capgemini
May 25, 2026
Full-time
Remote
Worldwide
$76,200 - $187,740 USD yearly
Verification Jobs, Level - Mid-Career

Job Title

ASIC Verification Engineer

Role Summary

Individual-contributor ASIC Verification Engineer responsible for planning and executing block- and subsystem-level verification for ARM-related IP (CPU Cortex-A v9, GPU Mali, Debug CSS600/CoreSight, etc.).

This is a 100% remote role. The engineer will own verification activities across the project lifecycle and collaborate with global teams to improve verification methodologies and design quality.

Experience Level

Mid-level — typically requires 5+ years of hands-on ASIC verification experience.

Responsibilities

Primary responsibilities include verification ownership, test development, and cross-team collaboration.

  • Develop and execute verification plans and test cases for ARM IP blocks.
  • Build and maintain UVM/SystemVerilog test environments and C-based test cases for ARM IP configuration and testing.
  • Perform coverage planning, coverage analysis, and debug failures at RTL and gate-level simulation (GLS).
  • Conduct specification and architectural reviews to align verification scope with design intent.
  • Debug complex issues and support design teams with root-cause analysis and fixes.
  • Collaborate with the global verification team to improve verification processes and tools.

Requirements

Must-have technical skills and practical experience; followed by concise nice-to-have items.

  • Must-have: 5+ years hands-on experience with modern verification methodologies including UVM/SystemVerilog, formal verification, constraint-random testing, assertions, and coverage-driven verification.
  • Must-have: Strong practical experience with ARM-related IPs (Cortex-A v9, Mali, CSS600/CoreSight).
  • Must-have: Experience designing and implementing C-based test cases and reusing vendor-provided test benches for ARM IPs.
  • Must-have: Experience with gate-level simulation and coverage analysis.
  • Nice-to-have: Experience creating UVM-based block-level environments and reusing them at subsystem level.
  • Nice-to-have: Ability to read RTL (SystemVerilog/Verilog/VHDL); experience with revision control and CI/CD workflows.
  • Nice-to-have: Strong communication, process documentation, and cross-team collaboration skills.

Education Requirements

Not specified.


About the Company

Company: Capgemini

Headquarters: Paris, France

Global consulting, technology and engineering services firm offering digital and business transformation, cloud, AI, and engineering/R&D services across industries. Employs around 340,000 people in 50+ countries and provides end-to-end solutions from strategy and design to engineering.

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Date Posted: 2026-05-25