ASIC Verification Engineer

Job Title

ASIC Verification Engineer

Role Summary

Individual-contributor verification engineer responsible for developing and owning verification for ARM-based SoC IP blocks (CPU, GPU, debug, interconnect). You will create verification plans, UVM environments, tests, and drive coverage and debug across the project lifecycle.

12-month engagement. Candidates anywhere in the United States who can work EST are acceptable. Role may require quarterly one-week travel to Paris. Knowledge of French is a plus.

Experience Level

Mid-level — typically 5+ years of hands-on ASIC/SoC verification experience.

Responsibilities

Deliver and maintain verification assets and provide engineering leadership for verification activities.

• Develop verification plans, UVM environments, and constraint-random testcases driven by golden models and ARM VIP.
• Implement tests covering AXI/APB interconnects, cache/coherency, DMA, interrupts, MMU and power-state behavior.
• Perform coverage analysis, debug RTL and test failures, and run gate-level simulations as required.
• Write and reuse C-based test programs to configure and exercise ARM IPs and integrate vendor testbenches when needed.
• Review specifications and architecture for ARM-related IP; provide feedback to improve design and verification quality.
• Collaborate with a global verification team to improve processes and verification effectiveness.

Requirements

Must-have technical skills, plus a few desirable items.

• 5+ years hands-on verification experience with UVM/SystemVerilog, constraint-random verification, assertions, and coverage-driven methodology.
• Experience with ARM-related IP: Cortex-A (A9 and newer), Cortex-M (M4/M55) families; familiarity with Cortex-A multi-core MMU-based systems, shared L2/private L1 caches, and cache coherency validation.
• Practical knowledge of interconnects (AXI/APB), DMA, interrupts, CoreSight/JTAG debug flows, and power-management features.
• Experience with formal verification techniques, coverage analysis, and gate-level simulation.
• Ability to author C-based testcases to exercise IP and reuse manufacturer-provided test benches.
• Available to work US Eastern Time; occasional travel (quarterly, ~1 week) to Paris may be required.
• Nice-to-have: French language ability.

Education Requirements

Not specified.

About the Company

Company: Lumiere Systems

Engineering services firm specializing in semiconductor and ASIC design and verification for ARM-based SoCs. Engages in full verification lifecycle (UVM/SystemVerilog, formal, gate-level simulation) and collaborates with global verification teams and client partners.