Capgemini logo

ASIC Verification Engineer

Capgemini
May 20, 2026
Full-time
Remote
Worldwide
$76,200 - $187,740 USD yearly
Verification Jobs, Level - Mid-Career

Job Title

ASIC Verification Engineer

Role Summary

Individual-contributor role responsible for verification of ARM-related IP blocks (CPU Cortex-A v9, GPU Mali, Debug CSS600/CoreSight, etc.).

Work remotely with global verification teams to develop verification plans, implement UVM/SystemVerilog environments and tests, perform coverage and gate-level analysis, and improve verification processes and quality.

Experience Level

Mid-level — proven experience (5+ years) in ASIC verification and related methodologies.

Responsibilities

Primary responsibilities include ownership of verification for core IP blocks and collaboration across teams.

  • Develop and execute verification plans for ARM IP blocks (CPU, GPU, debug components).
  • Design and implement test cases (including C-based tests) and UVM/SystemVerilog environments.
  • Perform coverage analysis, assertions, constraint-random verification, and gate-level simulation.
  • Debug functional and integration issues; support cross-team debugging and specification refinement.
  • Participate in specification and architectural reviews and drive quality improvements across the verification flow.
  • Collaborate with global teams to standardize and improve verification methodologies and processes.

Requirements

Must-have technical skills and experience followed by optional qualifications.

  • Must-have: 5+ years hands-on ASIC verification experience using UVM/SystemVerilog, constraint-random techniques, assertions, coverage-driven verification, and gate-level simulation.
  • Must-have: Strong, practical knowledge of ARM IPs: CPU (Cortex-A v9), GPU (Mali), Debug (CSS600, CoreSight), etc.
  • Must-have: Experience creating C-based test cases to configure and validate ARM IPs and reusing vendor-provided test benches.
  • Must-have: Experience with coverage analysis and verification metrics.
  • Nice-to-have: Experience building/reusing UVM environments from block to subsystem level.
  • Nice-to-have: Ability to read RTL (SystemVerilog, Verilog, VHDL); experience with revision control and CI/CD workflows.
  • Nice-to-have: Strong documentation, process-development, and communication skills; ability to work independently and across teams.

Education Requirements

Not specified.


About the Company

Company: Capgemini

Headquarters: Paris, France

Global consulting, technology and engineering services firm offering digital and business transformation, cloud, AI, and engineering/R&D services across industries. Employs around 340,000 people in 50+ countries and provides end-to-end solutions from strategy and design to engineering.

Capgemini logo

Date Posted: 2026-05-19