ASIC SoC Verification Lead

Role Summary

This position is focused on the verification of AMD’s custom silicon/ASIC designs, ensuring precision and functionality in both new and existing features, maintaining a bug-free final product.

Experience Level

Candidate must possess at least 8 years of experience in Design Verification with strong expertise in Verilog, System Verilog, C, and knowledge of UVM/OVM methodologies.

Responsibilities

Responsibilities include:

• Collaborating with various engineering teams to comprehend architecture verification needs.
• Creating detailed test plans derived from architectural specifications.
• Overseeing Digital Verification (DV) sign-off to guarantee design integrity.
• Providing support for debug operations and contributing to root-cause analysis for failures.
• Developing verification testbenches and environments tailored to SoC designs.
• Mentoring junior engineers and optimizing verification methodologies to improve team efficiency.

Requirements

Candidates must demonstrate:

• A deep understanding of SoC design and architecture.
• Experience with wireless protocol verification.
• Strong debugging capabilities with tools such as VCS and Verdi.
• Hands-on experience with UVM-based verification frameworks.
• Proficiency in scripting languages, including Perl, Python, and Shell.

Education Requirements

Specific educational qualifications were not detailed; however, a technical background in relevant engineering disciplines is essential for this role.