ASIC/SoC Design Engineer, RTL design for SoC IPs

Role Summary

Join AMD's Silicon Design team to design and develop cutting-edge IPs for next-generation embedded products. You will own the complete RTL design lifecycle from micro-architecture specification through production silicon, working on complex IP design.

Experience Level

Senior ASIC/SOC designer with proven expertise across the entire chip development lifecycle, excelling in Verilog RTL coding, timing closure, and physical design awareness.

Responsibilities

• Author detailed micro-architecture specifications and own complete Verilog RTL implementation of major IP blocks, ensuring compliance with PPA (Performance, Power, Area) targets and timing requirements.
• Drive design from concept through production silicon across all phases including specification, RTL coding, lint/CDC checks, synthesis, timing analysis, verification, physical design integration, and post-silicon validation.
• Develop and maintain timing constraints (SDC), perform static timing analysis (STA) using industry-standard tools, resolve timing violations, and collaborate with physical design to achieve timing closure.
• Integrate complex ASIC IP blocks into full-chip SOC environment, ensuring proper connectivity and compliance with industry-standard protocols.
• Partner with verification teams to ensure comprehensive functional coverage; implement design-for-test (DFT) and design-for-debug (DFD) features; participate in RTL quality reviews and signoff.
• Work closely with physical design engineers on floor planning, placement constraints, clock tree synthesis, and power grid design.
• Develop Python/Perl/Tcl scripts to automate repetitive tasks and enhance team efficiency throughout the design flow.
• Engage with architecture, verification, physical design, CAD, and post-silicon teams to resolve complex technical challenges.

Requirements

• Proven track record with 2+ production ASIC tape-outs in senior design roles.
• Expert-level Verilog RTL coding skills with deep understanding of synthesizable RTL constructs and coding best practices.
• Hands-on experience with the complete ASIC design flow: RTL → Synthesis → STA → Physical Design → Tape-out.
• Experience writing and debugging SDC timing constraints including multi-cycle paths and clock domain crossing constraints.
• Experience integrating complex IP blocks into SOC designs.
• Knowledge of industry-standard on-chip interconnect protocols (AMBA AXI/AHB/APB).

Education Requirements

Bachelor's or Master's degree in Electrical Engineering or Computer Engineering.