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ASIC RTL Design Engineer

Ericsson
May 19, 2026
Full-time
Remote friendly (Austin, Texas, United States)
Worldwide
RTL Design Jobs, Level - Mid-Career

Job Title

ASIC RTL Design Engineer

Role Summary

Work on Ericsson Silicon's ASIC IP organization to design and deliver production-quality RTL for ASICs used in 5G network infrastructure. This role covers RTL design, verification, 3rd-party IP integration, simulation, debug, and PPA optimization.

Hybrid work schedule; this position is not remote and requires on-site presence in the Austin, TX office as part of a cross-functional hardware and software engineering team.

Experience Level

Mid-level β€” several years of hands-on industry RTL design experience (exact years not specified).

Responsibilities

Primary responsibilities include:

  • Write and verify clean, production-quality RTL for block- and top-level designs.
  • Take designs from specification through to silicon implementation and CMOS circuitry.
  • Integrate 3rd-party IP and perform system-level integration and verification.
  • Perform simulation, debug, and PPA (power, performance, area) optimization on advanced process nodes.
  • Use EDA tools to design, verify, and lint RTL; drive CDC and static timing closure activities.
  • Collaborate with backend/synthesis teams to close on synthesis, area, and timing goals.
  • Work cross-functionally with architects, verification, and physical design engineers to deliver shipping silicon.

Requirements

Must-have technical skills and experience:

  • Hands-on RTL design experience at block and/or top level in industry.
  • Solid foundation in digital logic design.
  • Proficiency in SystemVerilog, Verilog, or VHDL.
  • Deep understanding of clock domain crossing (CDC) and static timing analysis (STA).
  • Experience with RTL linting and CDC tools (e.g., Synopsys SpyGlass or peers).
  • Strong scripting/programming skills in C/C++, TCL, and/or Python.
  • Familiarity with EDA toolchains and workflow; comfortable in Git and Linux environments.
  • Ability to collaborate with backend teams on synthesis, area, and timing closure.

Nice-to-have:

  • Experience with AMBA interfaces (APB, AXI, ACE-Lite, CHI).
  • Background in computer architecture or VLSI systems.
  • IP experience across SerDes, PCIe, ARM subsystems, DSPs, accelerators, or Ethernet.
  • Experience with Cadence, Mentor, or Synopsys tool ecosystems.

Education Requirements

Bachelor of Science (BS) in Electrical Engineering or Computer Engineering is specified.


About the Company

Company: Ericsson

Headquarters: Stockholm, Sweden

Ericsson is a Swedish multinational provider of telecommunications equipment, software, and services, specializing in network infrastructure, core and radio access solutions, and managed services for operators. The company is a global leader in 5G technologies and related research and development.

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Date Posted: 2026-05-18