ASIC Physical Design Staff Engineer

Role Overview

The ASIC Physical Design Staff Engineer position is critical for implementing advanced IP solutions at Synopsys. With a focus on leading design initiatives for DDR, HBM, and HBI protocols, you will ensure optimal performance and reliability of silicon products. This role requires collaboration with global teams to drive project success in a dynamic engineering environment.

Experience Level

This position requires a minimum of 5 years of experience in ASIC physical design or related engineering roles. Applicants must demonstrate expertise in EDA tools, as well as proficiency in timing closure processes.

Key Responsibilities

Your main duties will include:

• Integrating DDR, HBM, and HBI IPs with a focus on high-performance designs.
• Driving timing closure for designs operating above 2GHz.
• Leading the development of clock tree structures with optimal skew balancing.
• Mentoring junior engineers and contributing to a culture of knowledge sharing.
• Resolving complex design challenges independently.
• Providing updates to management on project status.

Qualifications

The ideal candidate should have:

• 5+ years of post-graduate experience in ASIC physical design.
• Proficiency with industry-standard EDA tools like Design Compiler, IC Compiler II, and PrimeTime-SI.
• Hands-on experience with DDR/HBM/HBI and understanding of clock trees.
• A proven ability to solve complex technical issues and lead projects.

Education Requirements

A relevant degree in Electrical Engineering, Computer Engineering, or a closely related field is required.