ASIC Physical Design Sr. Engineer

Role Summary

Join our Mixed-Signal IP organization as a Senior Engineer focused on the physical design and implementation of complex Mixed Signal IPs and test chips. You will be responsible for leading the physical implementation of high-speed interface IPs, ensuring adherence to project timelines and quality standards.

Experience Level

This position requires 2+ years of direct physical design experience, showcasing your abilities in the full design cycle from RTL to GDSII.

Responsibilities

• Lead the physical implementation of high-speed interface IPs from RTL to GDS, ensuring timing and physical sign-off.
• Collaborate with cross-functional teams to integrate and verify IP designs.
• Provide technical guidance and mentorship to team members.
• Continuously improve design methodologies and processes.

Requirements

• BE or MSEE with 2+ years of direct physical design experience.
• Proficiency in the full design cycle from RTL to GDSII.
• Strong understanding of IC design and implementation flows.
• Experience with PnR and sign-off skills (STA, PV, EMIR).
• Excellent problem-solving abilities and attention to detail.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field is required.