ASIC Physical Design Senior Staff Engineer

Job Title

ASIC Physical Design Senior Staff Engineer

Role Summary

Senior physical design engineer responsible for owning and optimizing RTL-to-GDSII flows for UCIE IP, including STA and signoff, IP integration, automation, and tape-out readiness. The role works across architecture, RTL, circuit, and SoC teams to deliver signoff-quality IP.

Primary mission: ensure robust, automated flows and tape-out deliverables that meet aggressive PPA and quality goals.

Experience Level

Senior — typically 9+ years of block-level physical design experience; experience with advanced nodes (7nm or below) is a plus.

Responsibilities

Core responsibilities focus on RTL-to-GDSII implementation, signoff, IP integration, automation, and tape-out tasks.

• Own and optimize RTL-to-GDSII flow for UCIE IP, including STA and signoff work.
• Perform floorplanning, placement & routing, timing closure, and IR-drop/EM mitigation.
• Integrate covercells, macros, and complex IP; ensure clean abutment and QA.
• Run and interpret LVS/DRC checks and prepare foundry checklists and tape-out views.
• Automate tool flows, debug tool/runtime issues, and document best practices for the team.
• Collaborate with architecture, RTL, circuit, and SoC teams on test-chip and IP development.

Requirements

Must-have technical skills and experience followed by preferred skills.

• Must-have: 9+ years in block-level physical design with demonstrated experience in P&R, timing closure, and signoff for tape-outs.
• Must-have: Strong practical experience with STA and signoff tools (PrimeTime) and physical implementation tools (IC Compiler II / Fusion Compiler).
• Must-have: Experience with LVS/DRC and power integrity tools and methodologies (ICV, RedHawk) and with IR-drop/EM analysis.
• Must-have: Experience integrating complex IP and managing tape-out deliverables and foundry checklists.
• Nice-to-have: Advanced-node (7nm or below) experience.
• Nice-to-have: Scripting and flow automation experience (Tcl, Python) to build and maintain repeatable flows.

Education Requirements

Not specified.

Apply: https://synopsys.avature.net/careers/Login?jobId=16727

About the Company

Company: Synopsys

Headquarters: Mountain View, California, United States

Synopsys is a global leader in electronic design automation (EDA) and semiconductor IP, providing software, IP, and services for silicon design, verification, IP integration, and security. The company helps customers design and verify complex chips and systems for advanced nodes and AI-driven products.