ASIC Physical Design Senior Staff Engineer

Job Title

ASIC Physical Design Senior Staff Engineer

Role Summary

Lead implementation of UCIe PHY blocks and related testchips through floorplanning, place-and-route, timing closure and tapeout on 5nm and more advanced nodes. Work on the full physical design flow and coordinate with verification, DFT, IP integration, foundry, and customer engineering teams.

Expect to drive technical decisions, pilot advanced-node flows, and mentor junior engineers while managing multiple concurrent tapeouts to meet PPA and schedule targets.

Experience Level

Senior - 5–15 years of hands-on ASIC physical design experience (guidance provided in posting).

Responsibilities

Accountable for end-to-end physical design of UCIe PHY blocks and testchips on leading-edge process nodes.

• Own floorplanning through GDS generation for IP blocks and testchips.
• Drive synthesis, placement, routing, timing closure, and physical verification using tools such as DC, PT, ICC2/FC, and ICV.
• Collaborate with verification, DFT, and integration teams to resolve issues and meet PPA and schedule targets.
• Lead design reviews, present tradeoff analyses, and make real-time floorplan/CT/waiver decisions.
• Pilot and document new physical-design flows and advanced-node methodologies.
• Mentor junior engineers on timing closure, physical verification, and ICC2 toolchain usage.
• Interface with foundry and customer engineering to resolve technology file, DRC/LVS, and silicon bring-up issues.

Requirements

Must-have technical skills and experience for successful performance in this role.

• 5–15 years of hands-on ASIC physical design experience (must).
• Multiple tapeouts and signoffs on 5nm or more advanced nodes; experience taking designs to GDS (must).
• Proficiency with industry tools and flows: Design Compiler (DC), PrimeTime (PT), ICC2/FC, and ICV (must).
• Proven ownership on SoC or IP tapeouts with accountability for signoff and PPA results (must).
• Strong understanding of FinFET behavior and advanced-node issues such as multi-patterning, electromigration, and IR drop (must).
• Experience working with DFT insertion, scan routing, and ATPG is a strong plus (nice-to-have).
• Exposure to UCIe, SerDes, or other high-speed interface IP is valuable but not required (nice-to-have).
• Demonstrated ability to lead technical discussions, make schedule-driven tradeoffs, and mentor junior staff (must).

Education Requirements

Not specified.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.